1. Field of the Invention
The present invention relates to an analog-to-digital converter.
2. Description of the Related Art
With the widespread use of digital equipment, an analog-to-digital (AD) converter for converting an analog signal into a digital signal has been used in various many fields.
Such an AD converter is known by a parallel AD converter that converts an incoming analog signal into an N-bit (N=n+m) digital signal in parallel, and a subranging AD converter that performs conversion into higher-order m bits and lower-order n bits, for example.
Such a subranging AD converter is considered superior to a parallel AD converter in terms of the smaller circuit size and less power consumption. As an example, refer to Patent Document 1 (JP-A-2004-7134).
Described now is a subranging AD converter for converting an analog signal into an N-bit digital signal.
Such a subranging AD converter is configured to include: a series resistance string, a higher-order conversion circuit, and a lower-order conversion circuit. The series resistance string equally divides the range between reference voltages, and generates 2N divided voltages at regular intervals. The higher-order conversion circuit generates higher-order m bits of a digital signal based on the 2m−1 divided voltages at regular intervals. The lower-order conversion circuit generates lower-order n bits of the digital signal based on the 2n divided voltages selected from the 2N divided voltages by referring to information provided from the higher-order conversion circuit. In the subranging AD converter, the higher- and lower-order conversion circuits convert an incoming analog signal into an N-bit digital signal.
The issue here is an offset voltage possibly caused to the analog signal retained by a sample hold circuit (not shown) during comparison in the higher- and lower-order conversion circuits. The offset voltage may degrade the AD conversion in terms of linearity at a border portion of the higher-order bits. As an example, refer to Patent Document 2 (JP-A-9-162738). Herein, the offset voltage is a difference between error voltages observed at the time of voltage retention for the analog signal in higher- and lower-order-bit comparators of the higher- and lower-order conversion circuits, respectively.
As such, in the subranging AD converter of a previous type, a divided voltage is provided with redundancy for use in the lower-order-bit comparator in consideration of such an offset voltage.
FIG. 10 shows such a subranging AD converter in which a divided voltage for use in the lower-order-bit comparator is provided with redundancy. In this AD converter 10, higher-order three bits are subjected to conversion by a higher-order conversion circuit 13, and lower-order three bits are subjected to conversion by a lower-order conversion circuit 14 so that an incoming analog signal is converted into a six-bit digital signal.
As shown in FIG. 10, the AD converter 10 is configured to include a divided voltage generation circuit 11, the higher-order conversion circuit 13, a MUX (multiplexer) 12, and the lower-order conversion circuit 14. The divided voltage generation circuit 11 is configured by ladder resistors for generating a plurality of divided voltages by dividing the range of predetermined voltages (Va-Vb). The higher-order conversion circuit 13 serves to convert an incoming analog signal into a digital signal of higher-order three bits. The MUX 12 is a switch circuit that selects, for output, three of the divided voltages provided by the divided voltage generation circuit 11. The lower-order conversion circuit 14 serves to convert the analog signal into a digital signal of lower-order three bits based on the three divided voltages provided by the MUX 12.
In the higher-order conversion circuit 13, input terminals on one side of higher-order-bit comparators COMP10-1 to COMP10-7 are respectively connected with seven divided voltages V10-1 to V10-7, and input terminals on the other side thereof are respectively connected with analog signals for conversion. The seven divided voltages V10-1 to V10-7 are those generated by the divided voltage generation circuit 11 equally dividing, into eight, the range between a lower-order reference voltage (VRB) and a higher-order reference voltage (VRT).
By these higher-order-bit comparators COMP10-1 to COMP10-7, the higher-order conversion circuit 13 generates a digital signal of higher-order three bits.
For use of divided voltage output to the lower-order conversion circuit 14, the MUX 12 makes a switch selection based on information provided by the higher-order conversion circuit 13, i.e., selects any one of switches SW10-1 to SW10-8, any one of switches SW11-1 to SW11-8, and anyone of switches SW12-1 to SW12-8. That is, the MUX 12 causes thus selected three switches to short circuit through control thereover, and outputs three divided voltages generated by the divided voltage generation circuit 11 to the lower-order conversion circuit 14.
The information provided by the higher-order conversion circuit 13 indicates the range of the voltage of an incoming analog signal, i.e., in which range the voltage of the analog signal is located between any two of the divided voltages V10-1 to V10-7. Assuming that when the voltage of an incoming analog signal is in the range between the divided voltages V10-2 and V10-3, information indicating as such is notified. In this case, based on such information provided by the higher-order conversion circuit 13, the MUX 12 selects the switches SW10-3, SW11-3, and SW12-3.
In this example, after the switch selection made based on the information provided by the higher-order conversion circuit 13, the MUX 12 is allowed to select the range of a voltage being the lowest voltage unit in the higher-order conversion circuit 13 plus a component of redundancy. Such a voltage unit denotes a voltage between any of the adjacent divided voltages V10-1 to V10-7, and hereinafter may be referred to as “LSB”. When the information provided by the higher-order conversion circuit 13 indicates that the voltage of an analog signal is in the range between the divided voltages V10-4 to V10-5, the lower-order conversion circuit 14 selects the switches SW10-5, SW11-5, and SW12-5, and causes these switches to short circuit. The lower-order conversion circuit 14 then selects, for the range between the divided voltages V10-4 and V10-5, a voltage range added with first and second components of redundancy, and an intermediate voltage therebetween for output to the lower-order-bit comparators COMP11-1 to COMP11-3. The first component of redundancy is higher than the divided voltage V10-5 by a predetermined value, and the second component of redundancy is lower than the divided voltage V10-4 by the predetermined value. The lower-order conversion circuit 14 then generates a digital signal of lower-order three bits with respect to an analog signal provided based on signals coming from the lower-order-bit comparators COMP11-1 to COMP11-3. Note here that the lower-order conversion circuit 14 is configured by the lower-order-bit comparators COMP11-1 to COMP11-3, and a known interpolation circuit that is not shown.